View LRS1341_167444.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LRS1341/LRS1342
Data Sheet
FEATURES
* Flash Memory and SRAM * Stacked Die Chip Scale Package * 72-ball CSP (FBGA072-P-0811) plastic package * Power supply: 2.7 V to 3.6 V * Operating temperature: -25C to +85C * Flash Memory - Access time (MAX.): 100 ns - Operating current (MAX.): The current for F-VCC pin - Read: 25 mA (tCYCLE = 200 ns) - Word write: 17 mA - Block erase: 17 mA - Deep power down current (the current for F-VCC pin): 10 A (MAX. F-CE F-VCC - 0.2 V, F-RP -0.2 V, F-VPP 0.2 V) - Optimized array blocking architecture - Two 4K-word boot blocks - Six 4K-word parameter blocks
Stacked Chip 16M Flash Memory and 2M SRAM
- Thirty-one 32K-word main blocks - Top/Bottom boot location versions - Extended cycling capability - 100,000 block erase cycles - Enhanced automated suspend options - Word write suspend to read - Block erase suspend to word write - Block erase suspend to read * SRAM - Access time (MAX.): 85 ns - Operating current (MAX.): - 45 mA - 8 mA (tRC, tWC = 1 s) - Standby current: 45 A (MAX.) - Data retention current: 35 A (MAX.)
DESCRIPTION
The LRS1341/LRS1342 is a combination memory organized as 1,048,576 x 16-bit flash memory and 131,072 x 16-bit static RAM in one package.
PIN CONFIGURATION
72-BALL FBGA INDEX TOP VIEW
1 A B C D E F G H NC NC
2 NC
3 NC A16
F-WE
4 A11 A8
F-RY/ BY
5 A15 A10 T1
T2
6 A14 A9 T3
T4
7 A13
8 A12
9 GND
10 NC
DQ7 DQ5
11 NC
12 NC
DQ15 S-WE DQ14 DQ13 DQ6 DQ4
GND F-WP
F-RP
DQ12 S-CE2 S-VCC F-VCC T5 DQ9 DQ10 DQ2 DQ8 DQ0 DQ3 DQ1
F-VPP F-A19 DQ11 NC
S-LB S-UB S-OE F-A18 NC NC F-A17 A5 A7 A4
A6 A0
A3 F-CE
A2
A1
S-CE1 NC NC NC
GND F-OE
NOTE: Two NC pins at the corner are connected.
LRS1342-1
Figure 1. LRS1341/LRS1342 Pin Configuration
Data Sheet
1
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
F-VCC F-A17 to F-A19 A0 to A16 F-CE F-OE F-WE F-RP F-WP
F-VPP
F-RY/BY GND 16M (x16) BIT FLASH MEMORY
DQ0 to DQ15
S-CE1 S-CE2 S-OE S-WE S-LB S-UB 2M (x16) BIT SRAM
S-VCC
LRS1342-2
Figure 2. LRS1341/LRS1342 Block Diagram
2
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Table 1. Pin Descriptions PIN A0 to A16 F-A17 to F-A19 F-CE S-CE1, S-CE2 F-WE S-WE F-OE S-OE S-LB S-UB F-RP DESCRIPTION Address Inputs (Common) Address Inputs (Flash) Chip Enable Input (Flash) Chip Enable Inputs (SRAM) Write Enable Input (Flash) Write Enable Input (SRAM) Output Enable Input (Flash) Output Enable Input (SRAM) SRAM Byte Enable Input (DQ0 to DQ7) SRAM Byte Enable Input (DQ8 to DQ15) Reset/Power Down (Flash) Block erase and Word Write: VIH or VHH Read: VIH or VHH Reset/Power Down: VIL Write Protect (Flash) Two Boot Blocks Locked: VIL (with F-RP = VHH Erase of Write can operate to all blocks) Ready/Busy (Flash) During an Erase or Write operation: VOL Block Erase and Word Write Suspend: HIGH-Z Deep Power Down: VOH Data Input/Outputs (Common) Power Supply (Flash) Power Supply (SRAM) Write, Erase Power Supply (Flash) Block Erase and Word Write: F-VPP = VPPLK All Blocks Locked: F-VPP < VPPLK Ground (Common) No Connection Test Pins (Should be Open) TYPE Input Input Input Input Input Input Input Input Input Input Input
F-WP
Input
F-RY/BY DQ0 to DQ15 F-VCC S-VCC F-VPP GND NC T1 to T5
Output Input/Output Power Power Power Power -- --
Data Sheet
3
LRS1341/LRS1342 Table 2. Truth Table1
FLASH Read Output Disable Write SRAM Standby Standby Standby Read Standby Output Disable Write Read Reset/Power Down Output Disable Write Standby Reset/Power Down Standby Standby F-CE L L L H H H H X X X X H X F-RP H H H H H H H L L L L H L F-OE L H H X X X X X X X X X X F-WE H H L X X X X X X X X X X L L L L L L L L H H H H H H H H See Note 4 S-CE1 S-CE2 S-OE X X X L H X L L H X L X X
Stacked Chip (16M Flash & 2M SRAM)
S-WE X X X H H X L H H X L X X
S-LB
S-UB
DQ0 DQ-7
DQ8 DQ15
NOTES 2, 3 3 2, 3, 5, 6
DOUT See Note 4 HIGH-Z DIN See Note 7 X H X H HIGH-Z HIGH-Z
See Note 7 X H X H HIGH-Z HIGH-Z
See Note 7 See Note 4 HIGH-Z HIGH-Z 3 3
See Note 4
NOTES: 1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics. 2. Refer to the `Flash Memory Command Definition' section for valid DIN during a write operation. 3. F-WP set to VIL or VIH. 4. SRAM standby mode. See Table 2a. Table 2a. MODE PINS S-CE1 H Standby (SRAM) X X S-CE2 X L X S-LB X X H S-UB X X H
5. Command writes involving block erase or word write are reliably executed when F-VPP = VPPH and F-VCC = 2.7 V to 3.6 V. Block erase or word write with VIH < RP < VHH produce spurious results and should not be attempted. 6. Never hold F-OE LOW and F-WE LOW at the same time. 7. S-LB, S-UB control mode. See Table 2b. Table 2b. MODE (SRAM) PINS S-LB L Read/Write L H S-UB L H L DQ0 - DQ7 DOUT/DIN DOUT/DIN HIGH-Z DQ8 - DQ15 DOUT/DIN HIGH-Z DOUT/DIN
Table 3. Command Definition for Flash Memory1
COMMAND Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write Resume BUS CYCLES REQUIRED 1 2 2 1 2 2 1 1 FIRST BUS CYCLE OPERATION Write Write Write Write Write Write Write Write
2
SECOND BUS CYCLE DATA FFH 90H 70H 50H 20H Write Write BA WA D0H WD Read Read IA XA ID SRD
3
ADDRESS XA XA XA XA BA WA XA XA
3
OPERATION2
ADDRESS3
DATA3
NOTES
4
5 5 5 5
40H or 10H B0H D0H
NOTES: 1. Commands other than those shown in table are reserved by SHARP for future device implementations and should not be used. 2. BUS operations are defined in Table 2. 3. XA = Any valid address within the device; IA = Identifier code address; BA = Address within the block being erased;
WA = Address of memory location to be written; SRD = Data read from status register, see Table 6; WD = Data to be written at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first); ID = Data read from identifier codes. 4. See Table 4 for Identifier Codes. 5. See Table 5 for Write Protection Alternatives.
4
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Table 4. Identifier Codes CODES Manufacture Code Device Code ADDRESS (A0 - A18) 00000H 00001H LRS1341 DATA (DQ0 - DQ7) B0H 48H LRS1342 DATA (DQ0 - DQ7) B0H 49H
Table 5. Write Protection Alternatives
OPERATION F-VPP F-RP F-WP EFFECT All blocks locked All blocks locked All blocks unlocked Two boot blocks locked All blocks unlocked
VIL
Block Erase or Word Write
X VIL VHH VIH VIH
X X X VIL VIH
> VPPLK
Table 6. Status Register Definition
WSMS 7 ESS 6 ES 5 WWS 4 VPPS 3 WWSS 2 DPS 1 R 0
SR.7 = Write State Machine Status (WSMS) 1 = Ready 0 = Busy SR.6 = Erase Suspend Status (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = Erase Status (ES) 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = Word Write Status (WWS) 1 = Error in Word Write 0 = Successful Word Write SR.3 = VPP Status (VPPS) 1 = F-VPP LOW Detect, Operation Abort 0 = F-VPP Okay SR.2 = Word Write Suspend Status (WWSS) 1 = Word Write Suspended 0 = Word Write in Progress/Completed SR.1 = Device Protect Status (DPS) 1 = F-WP and/or F-RP Lock Detected, Operation Abort 0 = Unlock SR.0 = Reserved for future enhancements (R)
NOTES: 1. Check RY/BY or SR.7 to determine block erase or word write completion. SR.6 - SR.0 are invalid while SR.7 = 0. 2. If both SR.5 and SR.4 are `1's after a block erase attempt, an improper command sequence was entered. 3. SR.3 does not provide a continuous indication of F-VPP level. The WSM interrogates and indicates the F-VPP level only after Block Erase or Word Write command sequences. SR.3 is not guaranteed to report accurate feedback only when F-VPP VPPH1, VPPH2. 4. The WSM interrogates the F-WP and F-RP only after Block Erase or Word Write command sequences. It informs the system, depending on the attempted operation, if the F-WP is not VIH or F-RP is not VHH. 5. SR.0 is reserved for future use and should be masked out when polling the status register.
Data Sheet
5
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
MEMORY MAPS
[A0 - A19] FFFFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000 [A0 - A19] FFFFF F8000 F7FFF F0000 EFFFF E8000 E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000 BFFFF B8000 B7FFF B0000 AFFFF A8000 A7FFF A0000 9FFFF 98000 97FFF 90000 8FFFF 88000 87FFF 80000 7FFFF 78000 77FFF 70000 6FFFF 68000 67FFF 60000 5FFFF 58000 57FFF 50000 4FFFF 48000 47FFF 40000 3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000
LRS1342-3
TOP BOOT 4K-WORD BOOT BLOCK 4K-WORD BOOT BLOCK 4K-WORD PARAMETER BOOT BLOCK 4K-WORD PARAMETER BOOT BLOCK 4K-WORD PARAMETER BOOT BLOCK 4K-WORD PARAMETER BOOT BLOCK 4K-WORD PARAMETER BOOT BLOCK 4K-WORD PARAMETER BOOT BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 0 1 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
LRS1342-13
32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK 32K-WORD MAIN BLOCK
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4K-WORD PARAMETER BOOT BLOCK 5 4K-WORD PARAMETER BOOT BLOCK 4 4K-WORD PARAMETER BOOT BLOCK 3 4K-WORD PARAMETER BOOT BLOCK 2 4K-WORD PARAMETER BOOT BLOCK 1 4K-WORD PARAMETER BOOT BLOCK 0 4K-WORD BOOT BLOCK 4K-WORD BOOT BLOCK BOTTOM BOOT 1 0
Figure 3. Bottom Boot for Flash Memory
Figure 4. Top Boot for Flash Memory
6
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply voltage Input voltage Operating temperature Storage temperature F-VPP voltage F-RP voltage SYMBOL VCC VIN TOPR TSTG F-VPP F-RP RATINGS -0.2 to +3.9 -0.2 to VCC +0.3 -25 to +85 -55 to +125 -0.2 to +14.0 -0.5 to +14.0 UNIT V V C C V V 1, 4, 5 1, 4, 5 NOTES 1, 2 1, 3, 4
NOTES: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F-VPP. 3. Except F-RP. 4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns. 5. +14.0 V overshoot is allowed when the pulse width is less than 20 ns.
RECOMMENDED DC OPERATING CONDITIONS
TA = -25C to +85C PARAMETER Supply voltage Input voltage SYMBOL VCC VIH VIL VHH MIN. 2.7 2.2 -0.2 11.4 TYP. 3.0 MAX. 3.6 VCC + 0.2 0.6 12.6 UNIT V V V V 1 2 3 NOTES
NOTES: 1. VCC is the lower one of S-VCC and F-VCC. 2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns. 3. This voltage is applicable to F-RP pin only.
PIN CAPACITANCE
TA = 25C, f = 1 MHz PARAMETER Input capacitance* I/O capacitance* SYMBOL CIN CI/O CONDITION VIN = 0 V VI/O = 0 V MIN. TYP. MAX. 20 22 UNIT pF pF
NOTE: *Sampled by not 100% tested.
Data Sheet
7
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
DC CHARACTERISTICS
TA = -25C to + 85C, VCC = 2.7 V to 3.6 V
PARAMETER Input leakage current Output leakage current SYMBOL ILI ILO CONDITION VIN = VCC or GND VOUT = VCC or GND F-CE = F-RP = F-VCC 0.2 V F-WP = F-VCC 0.2 V or F-GND 0.2 V F-CE = F-RP = VIH, F-WP = VIH or VIL Deep Power-Down Current ICCD F-RP = F-GND 0.2 V, IOUT (F-RY/BY) = 0 mA CMOS input, F-CE = F-GND, f = 5 MHz, IOUT = 0 mA TTL input, F-CE = F-GND, f = 5 MHz, IOUT = 0 mA F-VPP = 2.7 V to 3.6 V F-VPP = 11.4 V to 12.6 V F-VPP = 2.7 V to 3.6 V F-VPP = 11.4 V to 12.6 V F-CE = VIH F-VPP = F-VCC F-VPP > F-VCC F-RP = F-GND 0.2 V F-VPP = 2.7 V to 3.6 V F-VPP = 11.4 V to 12.6 V F-VPP = 2.7 V to 3.6 V F-VPP = 11.4 V to 12.6 V F-VPP = VPPH S-CE1, S-CE2 S-VCC - 0.2 V or S-CE2 0.2 V S-CE1 = VIH or S-CE2 = VIL S-CE1 = VIL, S-CE2 = VIH, VIN = VIL or VIH, tCYCLE = MIN., II/O = 0 mA S-CE1 = 0.2 V, S-CE2 = S-VCC - 0.2 V, VIN = S-VCC - 0.2 V, or 0.2 V tCYCLE = 1 s, II/O = 0 mA -0.2 2.2 IOL = 0.5 mA IOH = -0.5 mA 2.2 1.5 2.7 11.4 1.5 Unavailable F-WP 11.4 12.6 3.6 12.6 10 8 2 10 0.1 12 MIN. -1.5 -1.5 25 0.2 5 TYP.1 MAX. +1.5 +1.5 50 2 10 25 30 17 12 17 12 6 15 200 5 40 30 25 20 200 45 3 45 UNIT A A A mA A mA mA mA mA mA mA mA A A A mA mA mA mA A A mA mA 3, 4 3, 4 2 NOTES
Standby Current
ICCS
F-VCC
Read Current
ICCR
Word Write Current Block Erase Current Word Write Block Erase Suspend Current Standby or Read Current Deep Power-Down Current F-VPP Word Write Current Block Erase Current Word Write or Block Erase Suspend Current Standby Current
ICCW ICCE ICCWS ICCES IPPS IPPR IPPD IPPW IPPE IPPWS IPPES ISB ISB1
S-VCC Operation Current
ICC1 ICC2
8 0.6 VCC + 0.2 0.4
mA V V V V V V V V V 6 2 2 5
Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage (CMOS) F-VPP Lockout during Normal Operations F-VPP Word Write or Block Erase Operations F-VCC Lockout Voltage F-RP Unlock Voltage
VIL VIH VOL VOH1 VPPLK VPPH1 VPPH2 VLKO VHH
NOTES: 1. Reference values at VCC = 3.0 V and TA = +25C. 2. Includes F-RY/BY. 3. Automatic Power Savings (APS) for Flash Memory reduces typical ICCR to 3 mA at 2.7 VCC in static operation. 4. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH.
5. Block erases and word writes are inhibited when F-VPP VPPLK and not guaranteed in the range between VPPLK (MAX.) and VPPH (MIN.), and above VPPH (MAX.). 6. F-RP connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
8
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
FLASH MEMORY AC CHARACTERISTICS AC Test Conditions
PARAMETER Input pulse level Input rise and fall time Input and Output timing reference level Output load CONDITION 0 V to 2.7 V 10 ns 1.35 V 1TTL + CL (30 pF)
Read Cycle
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER Read Cycle Time Address to Output Delay F-CE to Output Delay* F-RP HIGH to Output Delay F-OE to Output Delay* F-CE to Output in LOW-Z F-CE HIGH to Output in HIGH-Z F-OE to Output in LOW Z F-OE HIGH to Output in HIGH-Z Output Hold from Address, F-CE or F-OE change, whichever occurs first SYMBOL tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH 0 0 20 0 45 MIN. 100 100 100 10 45 MAX. UNIT ns ns ns s ns ns ns ns ns ns
NOTE: *F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-CE without impact on tELQV.
Data Sheet
9
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
Write Cycle (F-WE Controlled)1
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER Write Cycle Time F-RP HIGH Recovery to F-WE going to LOW F-CE Setup to F-WE going LOW F-WE Pulse Width F-RP VHH Setup to F-WE going HIGH F-WP VIH Setup to F-WE going HIGH F-VPP Setup to F-WE going HIGH Address Setup to F-WE going HIGH Data Setup to F-WE going HIGH Data Hold from F-WE HIGH Address Hold from F-WE HIGH F-CE Hold from F-WE HIGH F-WE Pulse Width HIGH F-WE HIGH to F-RY/BY going LOW Write Recovery before Read F-VPP Hold from Valid SRD, F-RY/BY HIGH-Z F-RP VHH Hold from Valid SRD, F-RY/BY HIGH-Z F-WP VIH Hold from Valid SRD, F-RY/BY HIGH
2 2
SYMBOL tAVAV tPHWL tELWL tWLWH tPHHWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL tQVPH tQVSL
MIN. 100 10 0 50 100 100 100 50 50 0 0 0 30
MAX.
UNIT ns s ns ns ns ns ns ns ns ns ns ns ns
100 0 0 0 0
ns ns ns ns ns
NOTES: 1. Read timing characteristics during block erase and word write operations are the same as during read-only operations. Refer to AC Characteristics for Read Cycle. 2. Refer to the `Flash Memory Command Definition' section for valid AIN and DIN for block erase or word write.
10
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Write Cycle (F-CE Controlled)1
TA = -25C to +85C, VCC = 2.7 V to 3.6 V
PARAMETER Write Cycle Time F-RP HIGH Recovery to F-CE going to LOW F-WE Setup to F-CE going LOW F-CE Pulse Width F-RP VHH Setup to F-CE going HIGH F-WP VIH Setup to F-CE going HIGH F-VPP Setup to F-CE going HIGH Address Setup to F-CE going HIGH2 Data Setup to F-CE going HIGH2 Data Hold from F-CE HIGH Address Hold from F-CE HIGH F-WE Hold from F-CE HIGH F-CE Pulse Width HIGH F-CE HIGH to F-RY/BY going LOW Write Recovery before Read F-VPP Hold from Valid SRD, F-RY/BY HIGH-Z F-RP VHH Hold from Valid SRD, F-RY/BY HIGH-Z F-WP VIH Hold from Valid SRD, F-RY/BY HIGH SYMBOL tAVAV tPHEL tWLEL tELEH tPHEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL tQVPH tQVSL 0 0 0 0 MIN. 100 10 0 70 100 100 100 50 50 0 0 0 25 100 MAX. UNIT ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Read timing characteristics during block erase and word write operations are the same as during read-only operations. Refer to AC Characteristics for Read Cycle. 2. Refer to the `Flash Memory Command Definition' section for valid AIN and DIN for block erase or word write.
Block Erase and Word Write Performance
TA = -25C to +85C, VCC = 2.7 V to 3.6 V
SYMBOL tWHQV1 tEHQV1 PARAMETER Word Write Time 32K-word Block Word Write Time 4K-word Block Block Write Time 32K-word Block Block Write Time 4K-word Block tWHQV2 tEHQV2 tWHRZ1 tEHRZ1 tWHRZ2 tEHRZ2 Block Erase Time 32K-word Block Block Erase Time 4K-word Bock Word Write Suspend Latency Time to Read Erase Suspend Latency Time to Read VPP = 2.7 V to 3.6 V MIN. TYP. 55 60 1.8 0.3 1.2 0.5 7.5 19.3 8.6 23.6
1
VPP = 11.4 V to 12.6 V MIN. TYP.1 15 30 0.6 0.2 0.7 0.5 6.5 11.8 7.5 15 MAX.
MAX.
UNIT s s s s s s s s
NOTES 2 2 2 2 2 2
NOTES: 1. Reference values at TA = +25C and VCC = 3.0 V, VPP = 3.0 V. 2. Excludes system-level overhead.
Data Sheet
11
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
FLASH MEMORY AC CHARACTERISTICS TIMING DIAGRAMS
Device Address Selection Address Stable tAVAV
Standby ADDRESS
Data Valid
F-CE tEHQZ
F-OE tGHQZ
F-WE
tGLQV tELQV tGLQX tELQX HIGH Z Valid Output tAVQV HIGH Z tOH
DQ
F-VCC tPHQV
F-RP
LRS1342-4
Figure 5. Read Cycle Timing Diagram
12
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
1
2
3
4
5
6
ADDRESS
AIN
AIN
tAVAV tWHWL
tAVWH
tWHAX
F-WE tWLWH tDVWH tWHGL
F-OE
F-CE
tELWL
tWHEH tWHDX tWHQV1, 2, 3, 4 Data Valid SRD DIN tEHRL
DQ
HIGH-Z
DIN
DIN
tPHWL F-RY/BY tSHWH
tQVSL
F-WP
tPHHWH VHH VIH F-RP VIL VPPH F-VPP VPPLK tVPWH
tQVPH
tQVVL
VIL NOTES: 1. VCC power-up and standby. 2. Write block erase or word write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command.
LRS1342-5
Figure 6. Write Cycle Timing Diagram (F-WE Controlled)
Data Sheet
13
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
1
2
3
4
5
6
ADDRESS
AIN
AIN
tAVAV
tAVEH tEHAX
F-WE
tWLEL
tEHWH
tEHGL
F-OE tEHEL tEHQV1, 2, 3, 4
F-CE tELEH tDVEH tEHDX Data Valid SRD DIN tEHRL DIN
DQ
HIGH-Z tPHWL
DIN
F-RY/BY tSHEH tQVSL
F-WP
tPHHEH VHH F-RP VIH VIL VPPH F-VPP VPPLK VIL NOTES: 1. VCC power-up and standby. 2. Write block erase or word write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. tVPEH
tQVPH
tQVVL
LRS1342-6
Figure 7. Write Cycle Timing Diagram (F-CE Controlled)
14
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
RESET OPERATIONS
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER F-RP Pulse LOW Time (if F-RP is tied to VCC, this specification is not applicable). F-RP LOW to Reset during Block Erase or Word Write F-VCC 2.7 V to F-RP HIGH SYMBOL tPLPH tPLRZ tVPH 100 MIN. 100 23.6 MAX. UNIT ns s ns 1, 2 3 NOTES
NOTES: 1. If F-RP is asserted while a block erase or word write operation is not executing, the reset will complete with 100 ns. 2. A reset time tPHQV is required from the later of F-RY/BY going HIGH-Z, or F-RP going HIGH until outputs are valid. 3. When the device power-up, holding F-RP LOW minimum 100 ns is required after VCC has been in predefined range and also has been stable there.
HIGH Z F-RY/BY (R) VOL VIH VIL tPLPH
F-RP (P)
A. Reset During Read Array Mode
HIGH Z F-RY/BY (R) VOL tPLRZ
F-RP (P)
VIH VIL tPLPH
B. Reset During Block Erase or Word Write
2.7 V F-VCC VIL tVPH VIH VIL
F-RP (P)
C. F-RP Rising Timing
LRS1342-7
Figure 8. AC Waveform for Reset Operation
Data Sheet
15
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
SRAM AC ELECTRICAL CHARACTERISTICS AC Test Conditions
PARAMETER Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load*
NOTE: *Including scope and jig capacitance.
CONDITION 0.4 V to 2.7 V 5 ns 1.5 V 1TTL + CL (30 pF)
Read Cycle
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER
Read Cycle Time Address Access Time Chip Enable Access Time Byte Enable Access Time Output Enable to Output Valid Output hold from address change S-CE1, S-CE2 LOW to Output Active* S-OE LOW to Output Active* S-UB or S-LB LOW to Output in HIGH Impedance* S-CE1, S-CE2 HIGH to Output in HIGH Impedance* S-OE HIGH to Output in HIGH Impedance* S-UB or S-LB HIGH to Output in HIGH Impedance* S-CE1 S-CE2 S-CE1 S-CE2 S-CE1 S-CE2
SYMBOL
tRC tAA tACE1 tACE2 tBE tOE tOH tLZ1 tLZ2 tOLZ tBLZ tHZ1 tHZ2 tOHZ tBHZ
MIN.
85
MAX.
85 85 85 85 45
UNIT
ns ns ns ns ns ns ns ns ns ns ns
10 10 10 10 10 0 0 0 0 25 25 25 25
ns ns ns ns
NOTE: *Active output to HIGH impedance and HIGH impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
Write Cycle
TA = -25C to +85C, VCC = 2.7 V to 3.6 V PARAMETER
Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Enable to End of Write Address Setup Time Write Pulse Width Write Recovery Time Input Data Setup Time Input Data Hold Time S-WE HIGH to Output Active* S-WE LOW to Output in HIGH Impedance*
SYMBOL
tWC tCW tAW tBW tAS tWP tWR tDW tDH tOW tWZ
MIN.
85 75 75 75 0 65 0 35 0 5 0
MAX.
UNIT
ns ns ns ns ns ns ns ns ns ns
25
ns
NOTE: *Active output to HIGH impedance and HIGH impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
16
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
SRAM AC CHARACTERISTICS TIMING DIAGRAMS
tRC
ADDRESS tAA tACE1, 2
S-CE1 tLZ tHZ
S-CE2 tBE tHZ
S-UB, S-LB tBLZ tOE tBHZ
S-OE tOLZ tOHZ
DOUT
Data Valid tOH
NOTE: S-WE is HIGH for Read Cycle.
LRS1342-8
Figure 9. Read Cycle Timing Diagram
Data Sheet
17
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
tWC
ADDRESS tAW tCW
(NOTE 2)
S-CE1 tWR
S-CE2 tBW
(NOTE 3)
S-UB, S-LB tAS
(NOTE 4)
tWP
(NOTE 7)
tWR
(NOTE 5)
S-WE tWZ tOW
(NOTE 8)
DOUT tDW
(NOTE 6)
tDH
DIN NOTES: 1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE. A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH, S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end of write. 3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. 6. During this period, DQ pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or after S-WE going LOW, the outputs remain in HIGH impedance state. 8. If S-CE1 goes HIGH or S-CE2 goes LOW simultaneously with S-WE going HIGH or S-WE going HIGH, the outputs remain in HIGH impedance state.
Data Valid
LRS1342-9
Figure 10. Write Cycle Timing Diagram (S-WE Controlled)
18
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
tWC
ADDRESS tAW tAS
(NOTE 4)
tCW
(NOTE 2)
tWR
S-CE1 tWR
(NOTE 5)
S-CE2 tBW
(NOTE 3)
S-UB, S-LB tWP
(NOTE 7)
S-WE
DOUT
HIGH IMPEDANCE tDW
(NOTE 6)
tDH
DIN NOTES: 1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE. A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH, S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end of write. 3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. 6. During this period, DQ pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or after S-WE going LOW, the outputs remain in HIGH impedance state.
Data Valid
LRS1342-10
Figure 11. Write Cycle Timing Diagram (S-CE Controlled)
Data Sheet
19
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
tWC
ADDRESS tAW tCW
(NOTE 2)
S-CE1 tWR
S-CE2 tBW
(NOTE 3)
S-UB, S-LB tAS
(NOTE 4)
tWP
(NOTE 7)
tWR
(NOTE 5)
S-WE tWZ tOW
(NOTE 8)
DOUT tDW
(NOTE 6)
tDH
DIN NOTES: 1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE. A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH, S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end of write. 3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. 6. During this period, DQ pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or after S-WE going LOW, the outputs remain in HIGH impedance state. 8. If S-CE1 goes HIGH or S-CE2 goes LOW simultaneously with S-WE going HIGH or S-WE going HIGH, the outputs remain in HIGH impedance state.
Data Valid
LRS1342-11
Figure 12. Write Cycle Timing (S-UB, S-LB Controlled)
20
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
SRAM DATA RETENTION CHARACTERISTICS
TA = -25C to +85C
PARAMETER Data Retention Supply Voltage Data Retention Supply Current Chip Enable Setup Time Chip Enable Hold Time SYMBOL VCCDR ICCDR tCDR tR CONDITIONS S-CE2 0.2 V or S-CE1 VCCDR - 0.2 V VCCDR = 3V, S-CE2 0.2 V or S-CE1 VCCDR - 0.2 V 0 5 MIN. 2.0 TYP.1 MAX. 3.6 35 UNIT V A ns ms NOTES 2 2
NOTES: 1. Reference value at TA = 25C, S-VCC = 3.0 V. 2. S-CE1 VCC - 0.2 V, S-CE2 VCC - 0.2 V (S-CE1 controlled) or S-CE2 0.2 V (S-CE2 controlled).
Data Retention Mode S-VCC 2.7 V tCDR tR
2.2 V VCCDR S-CE1 VCCDR - 0.2 V S-CE1 0V NOTE: To control the data retention mode at S-CE1, fix the input level of S-CE2 between VCCDR and VCCDR - 0.2 V, or 0 V and 0.2 V, and during the data retention mode.
LRS1342-12
Figure 13. Data Retention Timing Diagram (S-CE1 Controlled)
Data Retention Mode S-VCC 2.7 V S-CE2 VCCDR tCDR tR
0.6 V S-CE2 0.2 V 0V
LRS1342-13
Figure 14. Data Retention Timing Diagram (S-CE2 Controlled)
Data Sheet
21
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
GENERAL DESIGN GUIDELINES Supply Power
Maximum difference (between F-VCC and S-VCC) of the voltage is less than 0.3 V.
Data Protection Through F-VPP
When the level of F-VPP is lower than F-VPPLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. For the lockout voltage refer to the `DC Characteristics' section.
Power Supply and Chip Enable of Flash Memory and SRAM
S-CE1 should not be LOW and S-CE2 should not be HIGH when F-CE is LOW simultaneously. If the two memories are active together, they may not operate normally because of interference noises or data collision on DQ bus. Both F-VCC and S-VCC need to be applied by the recommended supply voltage at the same time except SRAM data retention mode.
Data Protection During Voltage Transition
DATA PROTECTION THROUGH F-RP When the F-RP is kept LOW during power up and power down sequence, write operation on the flash memory is disabled, write protecting all blocks. For details of F-RP control refer to the `Flash Memory AC Electrical Characteristics' section.
Power Up Sequence
When turning on Flash memory power supply, keep F-RP LOW. After F-VCC reaches over 2.7 V, keep F-RP LOW for more than 100 ns.
DESIGN CONSIDERATIONS Power Supply Decoupling
To avoid a bad effect on the system by flash memory power switching characteristics, each device should have a 0.1 F ceramic capacitor connected between its VCC and GND and between its VPP and GND. LOW inductance capacitors should be placed as close as possible to package leads.
Device Decoupling
The power supply needs to be designed carefully because one of the SRAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash Memory. Note peak current caused by transition of control signals (F-CE, S-CE1, S-CE2).
VPP Trace on Printed Circuit Boards
Updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VPP Power Supply trace. Use similar trace widths and layout considerations given to the VCC power bus.
FLASH MEMORY DATA PROTECTION
Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate:
The Inhibition of Overwrite Operation
Please do not execute reprogramming `0' for the bit which has already been programmed `0'. Overwrite operation may generate unerasable bit. In case of reprogramming `0' to the data which has been programmed `1'. * Program `0' for the bit in which you want to change data from `1' to `0'. * Program `1' for the bit which has already been programmed `0'. For example, changing data from `1011110110111101' to `1010110110111100' requires `1110111111111110' programming.
Protecting Data in Specific Block
By setting a F-WP to LOW, only the boot block can be protected against overwriting. Parameter and main blocks cannot be locked. System program, etc., can be locked by storing them in the boot block. When a high voltage is applied to F-RP, overwrite operation is enabled for all blocks. For further information on setting/resetting of block bit, and controlling of F-WP and F-RP, refer to the `Command Definitions' section.
Power Supply
Block erase, full chip erase, word write and lock-bit configuration with an invalid VPP (see `DC Characteristics') produce spurious results and should not be attempted. Device operations at invalid VCC voltage product spurious results and should be attempted.
22
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
OUTLINE DIMENSIONS
FBGA072-P-0811
B
A INDEX
TOP VIEW 8.0 +0.2 -0 11.0 +0.2 -0 0.10 SIDE VIEW S S
(See Detail) 0.10 S
0.40 TYP.
DETAIL
1.1 TYP. 0.8 TYP. 0.4 TYP. C 1.4 MAX. 0.35 0.05 1.2 TYP. H BOTTOM VIEW G D F E D C B A 1 2 3 45 6 7 8 9 10 11 12 0.8 TYP. 0.4 TYP.
0.45 0.05
0.30 M 0.15 M
S AB S CD
72FBGA
NOTE: Dimensions are in mm.
Data Sheet
23
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
LIMITED WARRANTY
SHARP warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to SHARP in writing) or, (ii) if SHARP is unable to repair or replace, refund the purchase price of the Product upon its return to SHARP. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than Sharp. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will Sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. The above warranty is also extended to Customers of Sharp authorized distributors with the following exception: reports of failures of Products during the warranty period and return of Products that were purchased from an authorized distributor must be made through the distributor. In case Sharp is unable to repair or replace such Products, refunds will be issued to the distributor in the amount of distributor cost. SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied.
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpsma.com
(c)1999 by SHARP Corporation
SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Facsimile: (49) 40 2376-2232 http://www.sharpmed.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: +81-743-65-1321 Facsimile: +81-743-65-1532 http://www.sharp.co.jp
Reference Code SMA99092

▲Up To Search▲

Price & Availability of LRS1341

	To Download LRS1341 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .